Imec is a world-leading research and innovation center in nanoelectronics and digital technologies. In addition, we have shown its validity for 3D system scaling technologies, where the carrier wafer in de bonding process is replaced with a functional wafer (e.g., a logic wafer for enabling logic-on-logic 3D-SOCs), and the bottom dies are powered from the backside.” The results are derived from an IR drop modelling framework calibrated with experimental data.”Įric Beyne: “Our work shows that the backside can create a very dynamic design space with new design options that can help address shortcomings of traditional 2D IC scaling. The 2.5D MIMCAP boosts capacitance density with a factor of 4 to 5x, allowing a further improvement of the IR drop (32.1%/23.5% over the no-MIMCAP/2D-MIMCAP counterparts, respectively). Chen et al., we combined backside processing with the implementation of a 2.5D (i.e., pillar-like) metal-insulator-metal capacitor (MIMCAP), which serves as a decoupling capacitor. Eric Beyne, VP R&D of imec’s 3D System Integration : “In a 2022 VLSI paper by R. This ensures further scalability of the technology towards 2nm and beyond.”Īt the system level, backside power delivery promises to improve the overall power delivery performance, which increasingly suffers from a rise in power density and aggressive supply-voltage (or IR) drop.
The nTSVs land on BPRs with tight overlay control and are implemented at a tight pitch of 200nm without consuming any area of the standard cell. “This includes bonding of the wafer to a carrier wafer, wafer backside thinning and processing of ~320nm deep nTSVs. “With our test vehicle, in which nTSVs land on buried power rails defined in the wafer’s frontside, we show that the performance of the FinFETs is not degraded by backside processing,” adds Naoto Horiguchi. Naoto Horiguchi, Director CMOS Device Technology at imec: “We believe that combining backside power delivery with buried power rails – a structural scaling booster in the form of a local power rail that is buried deep in the chip’s front-end-of-line – is the most promising implementation scheme of a backside power delivery network in terms of scalability and performance.” Transmission electron microscopy TEM image showing scaled FinFET devices connected to the wafer’s backside (through nTSVs and BPR) and frontside (through BPR, VBPR and MOA). Veloso et al., imec demonstrates an advanced integration scheme with scaled FinFET devices connecting to both backside and frontside through buried power rails – a world’s first. At VLSI 2021, for example, imec for the first time showed backside connectivity through nTSVs landing on metal-1 pads in the wafer’s frontside.Īt this year’s VLSI, in the paper by A. Since imec’s first announcement in 2019, different implementations have been proposed. The concept of backside power delivery allows to decouple the power delivery network from the signaling metallization scheme in logic ICs, hence alleviating routing congestion in the back-end-of-line and delivering a power performance benefit. Additionally, imec demonstrated a performance boost by implementing a 2.5D MIMCAP in the backside. It also offers a system performance benefit by improving the power delivery. The novel routing scheme with decoupled power and signal wiring acts as a scaling booster for future logic technologies (2nm and beyond). The BPRs connect to scaled FinFET devices whose performance was not impacted by backside wafer processing. LEUVEN, Belgium, JT his week, at the 2022 IEEE VLSI Symposium on Technology and Circuits, imec, a world-leading research and innovation hub in nanoelectronics and digital technologies, presents the first experimental demonstration of a enabled through nano-through-silicon-vias (nTSVs) landing on buried power rails (BPRs). Since 1987 - Covering the Fastest Computers in the World and the People Who Run Them
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